The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a method and structure for high capacitance memory cells.
Electronic systems, such as microprocessor based computers, typically operate on data that is stored in electronic form in a memory device. The memory device stores the data at specified voltage levels in an array of cells. Conventionally, the voltage levels represent that the data is either a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0.xe2x80x9d In dynamic random access memory (DRAM) devices, for example, the cells store the data as a charge on a capacitor. When the data is read from the memory device, sense amplifiers detect the level of charge stored on a particular capacitor so as to produce a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d output based on the stored charge.
As the size of memory devices decreases, the capacitor in each cell covers a smaller surface area or footprint on the substrate, chip or wafer. If the structure of the capacitor is left unchanged, these smaller capacitors cannot store as much charge because the storage capacity of a typical capacitor is proportional to the size of its storage electrodes. Unfortunately, at some point, the capacitors become too small to store sufficient charge and sense amplifiers in the memory device are unable to differentiate between charge due to noise and the charge due to data stored in the cell. This can lead to errors in the output of a memory device making the memory device useless in the electronic system.
Conventionally, memory manufacturers have used one of two types of capacitors in DRAM devices. First, many manufacturers use xe2x80x9cstackedxe2x80x9d capacitors to store data for the memory cell. Stacked capacitors are typically formed from polysilicon and are positioned above the conventional working surface of the semiconductor chip or wafer on which the memory device is formed. A contact couples the capacitor to a transistor in the memory cell. Some manufacturers use xe2x80x9ctrenchxe2x80x9d capacitors instead of stacked capacitors. Trench capacitors are typically formed in a trench in the semiconductor wafer or chip. The trench is filled with polysilicon that acts as one plate of the capacitor. In this case, the semiconductor wafer or chip acts as the second plate of the capacitor.
Designers have experimented with various configurations of capacitors, both stacked and trench, to maintain the capacitance as the footprint available for the capacitor decreases. In the area of stacked capacitors, designers have used texturization, stacked V-shaped plates and other shaped plates to increase the surface area of the plates without increasing the footprint of the capacitor. For example, designers have developed techniques to produce hemispherical grains on the surface of one polysilicon plate of the stacked capacitor. This roughly doubles the storage capacity of the capacitor. Researchers have also described techniques for further increasing the surface area of the polysilicon plate, and thus the storage capacity of the capacitor, by using phosphoric acid to create pores in the polysilicon plate. See, Watanabe, A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs, Symposium on VLSI Technology, pp. 17-18, 1993. These micro-roughened polysilicon surface features have sizes of the order 100 A or 10 nm. With this technique, it is claimed that a 3.4 times increase in capacitance can be achieved.
One problem with the use of stacked capacitors is their positioning above the surface of the substrate. This positioning can interfere with the proper functioning of the equipment used to fabricate other parts of a larger circuit.
Conventionally, as the footprint available for trench capacitors has decreased, the manufacturers have used deeper trenches to maintain sufficient storage capacity of the trench capacitor. IBM has developed another technique in an attempt to maintain sufficient storage capacity as the footprint of the trench capacitor decreases. This technique uses an anodic etch to create pores in the single crystalline silicon in the trench of the trench capacitor. See, U.S. Pat. No. 5,508,542 (the ""542 Patent). One problem with this technique is the lack of control over the distribution of the pores in the surface of the single crystalline silicon. Thus, the ""542 Patent does not provide a technique that can be used reliably for large scale production of memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a realizable trench capacitor with increased surface area compared to prior art capacitors for use in high-density circuits such as dynamic random access memories.
The above mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A method and structure are provided to maximize the capacitance in memory cells.
In particular, an illustrative embodiment of the present invention includes a method for forming a trench capacitor. The method includes forming a trench with an interior surface in a semiconductor substrate. A self-structured mask is formed in the trench. The interior surface of the trench is etched to form an array of silicon pillars. The method further includes removing the self-structured mask and forming an insulator layer outwardly from the array of silicon pillars. A polycrystalline semiconductor plate is then formed outwardly from the insulator layer.
In another embodiment, a method for forming a memory cell with a trench capacitor is provided. The method includes forming a transistor with first and second source/drain regions, a body region and a gate in a layer of semiconductor material on a substrate. A trench is formed which has an interior surface in the layer of semiconductor material. A self-structured mask is formed on the interior surface in the trench. The interior surface of the trench is etched to form an array of asperities. The self-structured mask is removed and an insulator layer is formed outwardly from the array of asperities. A polycrystalline semiconductor plate is formed outwardly from the insulator layer in the trench such that the polycrystalline semiconductor plate forms one of the plates of the trench capacitor. The method further includes coupling the trench capacitor to one of the source/drain regions of the transistor.
In another embodiment, a memory cell is provided. The memory cell includes a lateral transistor formed in a layer of semiconductor material which extends outwardly from a substrate. The transistor includes a first source/drain region, a body region and a second source/drain region. A trench capacitor is formed. The trench capacitor includes a polycrystalline semiconductor plate formed in the trench which couples to the second source/drain region. A second plate is formed by the substrate. The substrate includes an array of silicon pillars formed using a self-structured mask. An insulator layer separates the polycrystalline semiconductor plate from the array of silicon pillars.
In another embodiment, a memory cell is provided. The memory cell includes a vertical transistor which is formed outwardly from a substrate. The transistor includes a first source/drain region, a body region and a second source/drain region that are vertically aligned. A surface of the second source/drain region includes an array of silicon pillars. The array is formed using a self-structured mask. The memory cell further includes a trench capacitor with a polycrystalline semiconductor plate. The polycrystalline semiconductor plate is formed in a trench that surrounds the array of silicon pillars on the surface of the second source/drain region of the transistor.
In another embodiment, a memory device is provided. The memory device includes an array of memory cells. Each memory cell includes an access transistor which couples to a trench capacitor. A first plate of the trench capacitor has a surface which includes an array of silicon pillars. A second plate of the trench capacitor is disposed adjacent to the first plate. A number of bit lines selectively couple to a number of the memory cells at a first source/drain region of the access transistor. A number of word lines are disposed substantially orthogonal to the bit lines and couple to gates of a number of access transistors. A row decoder couples to the word lines and a column decoder couples to the bit lines so as to selectively access the cells of the array.
Thus, a higher capacitance memory cell is provided. The memory cell includes an array of silicon pillars which are formed using a self-structured mask and dry etch technique. The resulting memory cells produce from a five to ten fold increase in the capacitance levels over those presently reported for micro roughened polysilicon structures. These results are achieved without requiring additional surface space on the memory chip. Thus, the present invention is ideally suited for use in DRAMs.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.